Non-volatile semiconductor memory devices based on metal-oxide-semiconductor field effect transistors (MOSFETs) were first proposed in 1967 (see Sze, "Physics of Semiconductor Devices" (Wiley-Interscience, pages 496-506, 2d Ed. 1981). These devices store a bit of information as the presence or absence of a quantity of electrical charge on a floating gate that is located so that the charge affects the threshold voltage of a MOSFET. Currently, MOSFET non-volatile memory devices include EPROMs, EEPROMs and Flash EEPROMs. EPROM (erasable programmable read only memory) cells store a bit of information as a quantity of electrons on a floating gate; the electrons are avalanche-injected into the floating gate from the drain end of the cell transistor channel and are erased for all cells simultaneously by photoemission under ultraviolet irradiation. The Floating gate Avalanche-injection MOS transistor is typically called a FAMOS transistor. The density of EPROMs had reached 1 megabite by 1984, but the inconvenience of the ultraviolet erase has led to the development of EEPROMs and Flash EEPROMs.
EEPROMs (electrically-erasable programmable read-only memories) both program and erase information for a single memory cell by tunneling charges through insulators: the FLOTOX version uses a floating gate as with an EPROM but with a thin tunneling oxide between the floating gate and the transistor drain; the textured poly version uses tunneling between three polysilicon gates with one of the gates a floating gate; and the MNOS version uses a stacked oxide and nitride gate insulators and stores charges in traps in the nitride and programs and erases by tunneling through the oxide to the channel region. See generally, S. Lai et al., "Comparison and Trends in Today's Dominant E.sup.2 Technologies," IEDM Tech Digest, p. 580 (1986).
Flash EEPROMs are hybrids that program in the manner of either EPROMs (avalanche-injection) or EEPROMs (tunneling) and erase in the manner of EEPROMs (tunneling) but with the erasure generally limited to bulk electrical erasure of the entire memory analogous to the ultraviolet light erasure of an EPROM.
The trend to larger scale integration has demanded small, highly packed memory cells with low power dissipation, and the desire for flexibility of multiple reprogramming has demanded durable tunneling oxides. Consequently, many variations of the basic EPROM, EEPROM and Flash EEPROM cells have been introduced. For example, McElroy, U.S. Pat. No. 4,373,248, shows EPROM cells in an array with a set of parallel continuous buried n+ diffusion lines in a silicon substrate acting as sources and drains (bitlines) for the floating gate cells with a second set of parallel continuous polysilicon lines over the floating gates acting as control gates (wordlines); the polysilicon lines are perpendicular to the buried diffusion lines. The disclosures of J. Esquivel et al., "High Density Contactless, Self-Aligned EPROM Cell Array Technology," 1986 IEDM Tech. Dig. 592, Mitchell, U.S. Pat. No. 4,597,060 and Sugiura et al., U.S. Pat. No. 4,451,904 also show buried bitlines and perpendicular polysilicon wordlines in an EPROM array.
Miyamoto, U.S. Pat. No. 4,642,673, discloses a floating gate EEPROM cell array with parallel continuous buried diffusion lines acting as control gates and each cell has a floating gate transistor plus a select transistor in series with the floating gate extending over a diffusion line; the source/drain contacts are to metal lines (bitlines and source lines) perpendicular to the diffusion lines, and gates for the select transistors are polysilicon lines (wordlines) parallel to the diffusion lines. Note that the series select transistor is added to avoid the case of an over-erased floating gate transistor going into depletion mode and conducting even with no voltage applied to the control gate.
D. Guterman, U.S. Pat. No. 4,590,504 discloses an EEPROM array with each cell having a buried source region connected to a buried ground line and a buried drain region including a remote drain portion for tunneling into the floating gate connected to a metal bitline plus parallel polysilicon control gate line and select transistor gate line.
F. Masuoka et al., "A 256K Flash EEPROM Using Triple Polysilicon Technology, 1985 ISSCC Technical Dig. 168, discloses a Flash EEPROM cell array with first level polysilicon erase lines, second level polysilicon floating gates and third level control gate lines (wordlines); the floating gate transistor and the select transistor are merged by having the floating gate over only a portion of the channel region. The transistor source connects to a diffusion line and the drain connects to a metal line over the polysilicon lines; the diffusion lines and the wordlines are parallel, and the erase lines and the metal lines are parallel and are perpendicular to the diffusion lines and wordlines. The floating gate is programmed by avalanche-injection as in an EPROM, and erasure of the floating gate is by tunneling to the adjacent erase line.
However, the known EEROMs and Flash EEPROMs have problems of large cell size limiting packing density, isolation and programmability for dense arrays of cells and complex processing.